The Series Load Resonant (SLR)
topology is a switching topology which is particularly well suited to
handling
short circuits,
and ensures soft switching of the devices when powering a load. The
gist of it is to create a resonant circuit of the primary side of a
transformer, in which an external capacitor, optional external
inductor, and the leakage inductance of the transformer itself form
this resonant circuit. The switching devices are then run at half of
the resonant frequency, but at only 25% duty cycle. This may seem odd
at first, but consider that 25% duty cycle at f_res/2 is equal to one
half cycle of the resonant circuit. So in effect each switch pair will
only be on for a half cycle of the resonant circuit, and the deadtime
between turning on alternate pairs is equal to one half cycle. What
this does is allow the resonant circuit to ring up for half a cycle,
and then ring down without having extra energy added to the circuit. In
the meantime, the switching device can turn off once the current has
reversed/completed a half cycle, which is effectivly soft switching.
See the oscilliographs below. In the first the repetition frequency is
a little short, so there is some deadtime between each resonant cycle.
It can be seen that the circuit rings up while one switch pair is open,
and the switches close once the current has reversed and flows in the
diodes.
In the second the repetition frequency has been tuned so no deadtime
exists between each resonant cycle, which gives the greatest power
throughput. Soft-switching is ensured in both cases.
[Left] Transformer secondary is shorted. On-time a bit short, and frequency lower than f_res/2. [Right] On-time set correctly, and frequency at
f_res/2.
The requirement of f_res/2 and
25% duty cycle isn't the actual demand to the switch timing, but just a
coincidence. To maintain soft switching it is only required that the
switches turn off sometime after the current has reversed, but before
it has time to reverse twice, ie before the next full cycle can begin.
The deadtime between each pair of switches is turned on needs only be
longer than one full cycle. You could run the system at f_res/4 or even
some odd multiple, with the only result being that less power is
transferred through the circuit. This is the case in the first
oscilliograph above. The time the switches are left on for
however (one half cycle of the resonant circuit) must remain the same.
The peak value the current will swing to when
the secondary is shorted is given by the supply voltage divided by the
surge impedance Z_0 of the primary side resonant circuit. When lightly
loaded the current can swing up to twice this value again. (The peak
current seen in the waveforms above was taken during earlier tests with
different component values, so if you try the formula below using the
values given in the schematic they won't add up.)
Because of the timing
requirements needed for soft switching, using a
duty cycle and frequency controller like the TL494 is not ideal. The
best controller for this type of application would allow for the
on-time to be set rather than duty cycle, and the repetition
rate/frequency set independently. However, the TL494 works just fine
once
tuned correctly, and as it was what I had at hand it was used
here. Power regulation of the SLR converter is best done by using pulse
repetition modulation, where maximum power is processed at
f_res/2, and any frequency lower than this results in less power. This
isn't exactly possible with the TL494, but I made an enable input using
one of the error amplifiers none the less. This allows for the
connection of a crude hysteresis controller when charging capacitors to
some defined voltage. The enable input needs to be pulled low to
disable the controller, so a single NPN transistor can be used for
electronic control.
Something I had originally
tried with this driver was to use UC3710T gate driver chips. I had
successfully used these before without issues, but in this driver I
experienced a sudden loss of gate drive which seemed to happen without
a specific cause. Shielding the driver seemed to help, but when trying
to charge a capacitor bank I would suddenly lose output from the
transformer, even though the driver was enabled.I eventually found that it was caused by latchup in the UC3710Ts, a problem some other people have experienced in the past.
Rather than attempt to fix an inherently flawed GDT driver design, I
simply changed over to UCC3732x gate drivers which have been used in
SSTCs for years. This fixed the problem immediately, even without
shielding the driver. I will not be usingUC3710Ts in any future designs, and recommend they are replaced in any old designs where present.
Updated SLR Driver
01.12.2022
I recently pulled this project from the closet, along with my microwave oven capacitor bank.
Looking over what went wrong last time, I decided to start with making a proper regular input
for the SLR driver. At the same time, I figured I could right a few wrongs in the previous driver
design. The new features I wanted were easier/independent tuning of frequency and on-time, along
with a correctly synchronized pulse-by-pulse enable input. The enable input shall not interrupt
an on-going cycle, and should also remember what the last cycle was, to prevent flux-walking in the
core from consistently disabling only one side of the pulse train. With this in place I should be
able to regulate the SLR driver care-free from a relatively high frequency PWM source, providing
semi-analog power control of the inverter. This all works out to a lot of digital logic however,
which would be rather cumbersome to implement using discrete ICs. Microcontrollers are too slow,
which means I can finally use a CPLD! I chose a Xilinx XCR3032XL, due to the nice package size
available, and the low number of macro cells needed for the design. During the component shortage
I wasn't able to acquire any Altera chips, but in the end I'm glad I went for Xilinx. The development
environment is nice and easy to use, and 3rd party JTAG units can be found for a decent price.
The circuit is essentially built around a Schmitt trigger rc oscillator, with diodes serving
to steer the on and off times independently. This oscillator generates the system clock. I've
also included an auxiliary clock, in case I needed to introduce dead-time or other fine-tuning
applications such as noise reduction with a digital filter. However none of that was needed in
the end, so it can be omitted. The system clock is fed into the CPLD, which splits it so each
pulse only triggers each gate drive output alternately. Parallel to this the interrupter input
is sent to the CPLD through the remaining Schmitt triggers, to ensure a noise free signal.
See the packaged KiCad project here for schematics, and PCB.
The driver was placed in a shielded container, which was 3D printed and then wrapped with
aluminium tape. The half-bridge and transformer both generate enough interference that the
sensitive CPLD wouldn't be very happy.
CPLD Firmware and function
While designing the CPLD logic I used Falstad's circuit simulator quite actively, as it provides a nice and simple way to mix analog and digital design. After some trial
and error I landed on a logical design, which I could implement in Verilog or VHDL. The interrupt signal
goes through a D-latch, where the clock source for the latch comes from a circuit which is high any time the currently active side changes. This means the interrupter signal retains it's value for one whole cycle,
and only changes value on a cycle by cycle basis, thus preventing one side being favored during interruption.
This prevents flux walking. The synchronized interrupter signal is fed to an AND gate for each gate driver,
where the second input of the AND gate is a signal indicating which gate driver's turn it is. The turn selection
signal is simply a T-latch which toggles for every system clock pulse. See the schematic below, though I find
the VHDL code easier to understand.
-----------------------------------------------------------------------------------------------
--
-- SLR Converter Pulse Controller Module
-- Eirik Taylor, 04.06.2022
--
--
-- Synchronizes output pulses with an incoming enable signal,
-- and ensures drive is alternated between each output, even after
-- enable is used. Application is high speed interruption of drive
-- pulses.
--
-----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity slr_pulse_controller is
port (
drive_clk : in STD_LOGIC;
enable : in STD_LOGIC;
gateA_drv : out STD_LOGIC;
gateB_drv : out STD_LOGIC;
gateA_en : out STD_LOGIC;
gateB_en : out STD_LOGIC
);
end slr_pulse_controller;
architecture Behavioral of slr_pulse_controller is
-- Dummy signal
signal rst: STD_LOGIC;
-- Interrupt signals
signal enable_syncd: STD_LOGIC;
-- Last interrupted side memory
signal pulse_active_side: STD_LOGIC;
signal lastLatched_A : STD_LOGIC;
signal lastLatched_B : STD_LOGIC;
-- Output signals
signal gateEnable_A: STD_LOGIC;
signal gateEnable_B: STD_LOGIC;
signal activeSide_A: STD_LOGIC;
signal activeSide_B: STD_LOGIC;
begin
-- Dummy reset signal
rst <= '1';
-- Driver enable outputs are always high. Enable handled internally
-- to avoid glitches from delays.
gateA_en <= '1';
gateB_en <= '1';
gateA_drv <= drive_clk and gateEnable_A;
gateB_drv <= drive_clk and gateEnable_B;
-- Only enable a side if it's it's turn, and the external enable signal is high
gateEnable_A <= activeSide_A and enable_syncd;
gateEnable_B <= activeSide_B and enable_syncd;
--
pulse_active_side <= (lastLatched_A and activeSide_A) or
(lastLatched_B and activeSide_B);
-- Connect the T-latches
drive_leg_toggle_t_latch : entity work.t_latch
port map (
rst => rst,
clk => drive_clk,
Q => activeSide_A,
nQ => activeSide_B
);
last_interrupted_side_toggle_t_latch : entity work.t_latch
port map (
rst => rst,
clk => enable_syncd,
Q => lastLatched_A,
nQ => lastLatched_B
);
-- Synchronize the interruption signal with the clock, and with
-- the last interrupted side
enableSyncProcess : process (pulse_active_side, rst)
begin
if (rst = '0') then
enable_syncd <= '0';
elsif (rising_edge(pulse_active_side)) then
enable_syncd <= enable;
end if;
end process;
end Behavioral;
A major part of this project was just designing the transformer
itself.
From before I had the "Big mo-fo" transformer suspended in oil, and
simply run it using a hard switching inverter. The resulting voltage
spikes
from doing so made it almost impossible to insulate the transformer
properly,
and as a result it would often arc over to the core and burn off small
fragments of ferrite. This was even when under oil! It only felt good
to dismount the old
transformer, clean the oil from the core, and begin working on it from
scratch with a new design. Having acquired a 3D printer, it was
suddenly easy to create a
perfect core former to wind the primary on, and also hold the core
pieces together. I initially spent a lot of time calculating the
required number of turns and corresponding loss density in the core,
but once I started testing with the actual transformer I found it was
not the limiting factor in terms of losses. As things stand now, the
transformer may only rise 1 degree above room temperature in the time
it takes the secondary winding and external inductor to raise by 20
degress. I would also recommend you to wind the external inductor using
litz wire, if long run times are needed. The exact core I used was a
"EPCOS Core Set u/93/152/30" which
consists of two large U cores, material type N27. The number of primary
turns is 12, and the secondary consists of 1 layer of 0.25mm wire wound
on a 75mm diameter former. There are ca 225 turns on the secondary, and
the output voltage has been measured to 6kV peak. The secondary has
been placed above the primary winding in an attempt to minimize the
leakage inductance.
One may wonder why to minimize this "free" inductance, when it could
instead contribute to the total inductance on the primary side. The
reason I see for this is so that one has greater control over the power
delivered by the system. The peak current is given by the surge
impedance as shown above, and this again will depend on the inductance
and capacitance. If the leakage inductance is too large, the size of
the capacitor required to bring the surge impedance down to the desired
value may also bring the resonance frequency all the way into the
audible region. In addition to possible saturation problems at low
frequencies, ear splitting squeals from a transformer running 10+kVA is
no joke!
The 3D printed parts for the transformer were designed using OpenSCAD,
so they are completely parametric. They can be downloaded here,
and adapted to most transformer sizes.
Disclaimer:
I do not take responsibility for any injury, death, hurt ego, or other
forms of personal damage which may result from recreating these
experiments. Projects are merely presented as a source of inspiration,
and should only be conducted by responsible individuals, or under the
supervision of responsible individuals. It is your own life, so proceed
at your own risk! All projects are for noncommercial use only.
This work is licensed under a
Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
